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[/] [rise/] [trunk/] [vhdl/] - Rev 135

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Rev	Log message	Author	Age	Path
135	uart_address_0 was a latch -> changed	ustadler	6362d 10h	/rise/trunk/vhdl/
134	Added second test program for testing uart.	jlechner	6362d 10h	/rise/trunk/vhdl/
132	Added test program for testing uart.	jlechner	6362d 12h	/rise/trunk/vhdl/
131	Changed high active resets to low active ones.	jlechner	6362d 12h	/rise/trunk/vhdl/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6362d 13h	/rise/trunk/vhdl/
127	Changed high active resets to low active ones.	jlechner	6362d 13h	/rise/trunk/vhdl/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6362d 19h	/rise/trunk/vhdl/
125	Fixed vhdl bugs	trinklhar	6362d 19h	/rise/trunk/vhdl/
124	Assigned UART signals to ports on top-level entity	trinklhar	6362d 19h	/rise/trunk/vhdl/
123	Removed UART again	trinklhar	6362d 20h	/rise/trunk/vhdl/
122	Removed UART again again	trinklhar	6362d 20h	/rise/trunk/vhdl/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6362d 20h	/rise/trunk/vhdl/
120	Added UART module to memory entity	trinklhar	6362d 20h	/rise/trunk/vhdl/
119	Uart wieder ausgebaut	trinklhar	6363d 15h	/rise/trunk/vhdl/
118	insert Uart address constant	trinklhar	6363d 15h	/rise/trunk/vhdl/
117	Uart im mem_stage	trinklhar	6363d 15h	/rise/trunk/vhdl/
116	writes to uart when write to reg 0	trinklhar	6364d 22h	/rise/trunk/vhdl/
115	* empty log message *	trinklhar	6365d 12h	/rise/trunk/vhdl/
114	Uart 0.3	trinklhar	6366d 16h	/rise/trunk/vhdl/
113	Uart reset funkt	trinklhar	6366d 17h	/rise/trunk/vhdl/

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[/] [rise/] [trunk/] [vhdl/] - Rev 135

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