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[/] [rise/] [trunk/] [vhdl/] - Rev 148

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Rev	Log message	Author	Age	Path
148	New directory structure.	root	5601d 21h	/rise/trunk/vhdl/
144	- IF stage now uses autogenerated VHDL files.	cwalter	6376d 08h	/trunk/vhdl/
142	- Added gap between characters sent and changed last character to CR.	cwalter	6376d 08h	/trunk/vhdl/
141	- Added delay between characters.	cwalter	6376d 08h	/trunk/vhdl/
140	- Test bench for RISE with UART.	cwalter	6376d 08h	/trunk/vhdl/
135	uart_address_0 was a latch -> changed	ustadler	6377d 06h	/trunk/vhdl/
134	Added second test program for testing uart.	jlechner	6377d 06h	/trunk/vhdl/
132	Added test program for testing uart.	jlechner	6377d 08h	/trunk/vhdl/
131	Changed high active resets to low active ones.	jlechner	6377d 08h	/trunk/vhdl/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6377d 08h	/trunk/vhdl/
127	Changed high active resets to low active ones.	jlechner	6377d 08h	/trunk/vhdl/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6377d 15h	/trunk/vhdl/
125	Fixed vhdl bugs	trinklhar	6377d 15h	/trunk/vhdl/
124	Assigned UART signals to ports on top-level entity	trinklhar	6377d 15h	/trunk/vhdl/
123	Removed UART again	trinklhar	6377d 16h	/trunk/vhdl/
122	Removed UART again again	trinklhar	6377d 16h	/trunk/vhdl/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6377d 16h	/trunk/vhdl/
120	Added UART module to memory entity	trinklhar	6377d 16h	/trunk/vhdl/
119	Uart wieder ausgebaut	trinklhar	6378d 11h	/trunk/vhdl/
118	insert Uart address constant	trinklhar	6378d 11h	/trunk/vhdl/

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[/] [rise/] [trunk/] [vhdl/] - Rev 148

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