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[/] [rise/] [trunk/] [vhdl/] - Rev 40

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40 - Added seperate memory output vector to MEM_WB_REGISTER.
- Added status register to MEM_WB_REGISTER.
jlechner 6374d 13h /rise/trunk/vhdl/
39 - Added wr_enable signals for imem and dmem
- Changed signals for register lock unit (this concerns id-stage and write-back-stage)
jlechner 6374d 13h /rise/trunk/vhdl/
38 Memory output signal is now passed on asynchronously to write back stage. jlechner 6374d 13h /rise/trunk/vhdl/
37 Applied VHDL indent. jlechner 6374d 13h /rise/trunk/vhdl/
36 - Testbench for RISE. cwalter 6374d 13h /rise/trunk/vhdl/
35 - Testbench for register file. cwalter 6374d 13h /rise/trunk/vhdl/
34 - Filex have been renamed to have tb prefix. cwalter 6374d 13h /rise/trunk/vhdl/
33 - Fixed process sensitivity list. cwalter 6374d 14h /rise/trunk/vhdl/
32 - When this stage asserts stall_out it must clear the input for the next
stage.
- Fixed process sensitivity list.
cwalter 6374d 14h /rise/trunk/vhdl/
31 - Added PC_RESET_VECTOR constant. cwalter 6374d 16h /rise/trunk/vhdl/
30 - Top level testbench for RISE. cwalter 6374d 16h /rise/trunk/vhdl/
29 - Initial version of IF stage with dummy instructions. cwalter 6374d 16h /rise/trunk/vhdl/
28 Added new register write enable signals. jlechner 6376d 09h /rise/trunk/vhdl/
27 Added new register write enable signals to component instantiation of register_file and wb_stage. jlechner 6376d 09h /rise/trunk/vhdl/
26 Applied VHDL indent. jlechner 6376d 09h /rise/trunk/vhdl/
25 netlist file for the memories
is needed for IMEM and DMEM
ustadler 6377d 09h /rise/trunk/vhdl/
24 4k Data Instruction for Spartan 3 (Block RAM)
Added write enable to the entity
ustadler 6377d 09h /rise/trunk/vhdl/
23 4k Data Memory for Spartan 3 (Block RAM)
Added write enable to the entity
ustadler 6377d 09h /rise/trunk/vhdl/
22 testbench für die register file ustadler 6377d 23h /rise/trunk/vhdl/
21 überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt ustadler 6378d 10h /rise/trunk/vhdl/

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