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[/] [rise/] [trunk/] [vhdl/] - Rev 58

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Rev	Log message	Author	Age	Path
58	- lr_enable signal in component wb_state should have direction out.	cwalter	6516d 15h	/rise/trunk/vhdl/
57	- applied indenting tool.	cwalter	6516d 16h	/rise/trunk/vhdl/
56	new sensitivity list	ustadler	6516d 16h	/rise/trunk/vhdl/
55	- clear_out must be initialized to '0'.	cwalter	6516d 17h	/rise/trunk/vhdl/
54	- Changed reset delay.	cwalter	6516d 17h	/rise/trunk/vhdl/
53	- Removed unused constant COND_NONE.	cwalter	6516d 17h	/rise/trunk/vhdl/
52	- stall_out must be initialized to '0'	cwalter	6516d 17h	/rise/trunk/vhdl/
51	- stall_out logic has moved to synchronous process.	cwalter	6516d 17h	/rise/trunk/vhdl/
50	- Added assembler example. - Added logic for stall_in. pc_next must not be updated on stall.	cwalter	6516d 17h	/rise/trunk/vhdl/
49	data can be ead asynchronous, data is written with the rising edge of the clk	ustadler	6516d 18h	/rise/trunk/vhdl/
46	- Added constant for RESET_VECTOR.	cwalter	6516d 22h	/rise/trunk/vhdl/
45	- Fixed latch for pc_next.	cwalter	6517d 14h	/rise/trunk/vhdl/
44	- Added another version of a register file which is a bit simplier.	cwalter	6517d 14h	/rise/trunk/vhdl/
43	Correct implementation of necessary unlocking signals that are conncted to register locking unit.	jlechner	6517d 14h	/rise/trunk/vhdl/
42	Modified input signals for register locking (testbench modifications): Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6517d 14h	/rise/trunk/vhdl/
41	Modified input signals for register locking: Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6517d 14h	/rise/trunk/vhdl/
40	- Added seperate memory output vector to MEM_WB_REGISTER. - Added status register to MEM_WB_REGISTER.	jlechner	6517d 14h	/rise/trunk/vhdl/
39	- Added wr_enable signals for imem and dmem - Changed signals for register lock unit (this concerns id-stage and write-back-stage)	jlechner	6517d 14h	/rise/trunk/vhdl/
38	Memory output signal is now passed on asynchronously to write back stage.	jlechner	6517d 14h	/rise/trunk/vhdl/
37	Applied VHDL indent.	jlechner	6517d 14h	/rise/trunk/vhdl/

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[/] [rise/] [trunk/] [vhdl/] - Rev 58

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