URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 8

Rev	Log message	Author	Age	Path
8	Implementation of execute stage and register lock unit. Some changes im RISE package.	jlechner	6399d 19h	/rise/trunk/vhdl/
7	- initial version of instruction decode stage testbench.	cwalter	6418d 12h	/rise/trunk/vhdl/
6	- applied VHDL source code indenter.	cwalter	6418d 12h	/rise/trunk/vhdl/
5	- correct register address width is 4 bit and not 5 bit. - added constants for OPCODES, COND and SR.	cwalter	6418d 12h	/rise/trunk/vhdl/
4	- added decode for rX, rY, rZ. - added decode for opcodes.	cwalter	6418d 12h	/rise/trunk/vhdl/
2	Initial commit of project	jlechner	6424d 15h	/rise/trunk/vhdl/