URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] - Rev 39

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Rev	Log message	Author	Age	Path
39	- updated assembler plus sample files	robfinch	3851d 14h	/rtf65002/trunk/
38	- updated to support the 65c816 opcodes	robfinch	3851d 14h	/rtf65002/trunk/
37	- latest documentation	robfinch	4000d 09h	/rtf65002/trunk/
36	- missing TRB/TSB instructions in 32 bit mode added	robfinch	4000d 09h	/rtf65002/trunk/
35	- several bug fixes - mul,mod,div immediates mode than 8 bits - page two opcode fix on cache miss - setting upper pc bits in emulation mode (store)	robfinch	4047d 02h	/rtf65002/trunk/
34	- latest bootrom.asm - and assembler	robfinch	4057d 16h	/rtf65002/trunk/
33	- most recent docs	robfinch	4057d 16h	/rtf65002/trunk/
32	- many changes - new instructions - code reorganization	robfinch	4057d 16h	/rtf65002/trunk/
31	- miscellaneous updates - unimplemented instruction vector -	robfinch	4067d 14h	/rtf65002/trunk/
30	- added additional branches - modified the pc increment - modified interrupts, all vector through BRK - registered some decodes - added SUPPORT macros to allow core trimming	robfinch	4067d 14h	/rtf65002/trunk/
29	- updated assembler, increased instruction support	robfinch	4073d 09h	/rtf65002/trunk/
28	- updated bootrom,	robfinch	4073d 09h	/rtf65002/trunk/
27	- most recent doc	robfinch	4074d 16h	/rtf65002/trunk/
26	- latest bootrom.asm - fixes to assembler	robfinch	4074d 16h	/rtf65002/trunk/
25	- add EXEC and ATNI instructions - fix store byte zero page indexed - fix break instruction	robfinch	4074d 16h	/rtf65002/trunk/
24	- fixes to assembler	robfinch	4080d 13h	/rtf65002/trunk/
23	- added subtract immediate from sp - added stack relative addressing mode - added move positive, move negative instructions - fix: TSA instruction	robfinch	4080d 13h	/rtf65002/trunk/
22	- fix indirect load	robfinch	4082d 03h	/rtf65002/trunk/
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	4082d 09h	/rtf65002/trunk/
20	- greater separation of emulation and native mode in source code - fix instruction buffer fetch for non-cached accesses - fix the sta (d),y instruction	robfinch	4083d 15h	/rtf65002/trunk/

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Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] - Rev 39

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