URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] - Rev 21

Rev	Log message	Author	Age	Path
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	4081d 23h	/rtf65002/trunk/rtl/
20	- greater separation of emulation and native mode in source code - fix instruction buffer fetch for non-cached accesses - fix the sta (d),y instruction	robfinch	4083d 05h	/rtf65002/trunk/rtl/
19	- added multibit shifts - added eight bit CMP instruction	robfinch	4084d 04h	/rtf65002/trunk/rtl/
13	- fix overflow in immediate mode - fix bit instruction N,V setting - add vector base register, modified interrupt vectoring	robfinch	4085d 04h	/rtf65002/trunk/rtl/
12	- added LFSR and TICK count special registers - added MUL/DIV/MOD instructions	robfinch	4086d 04h	/rtf65002/trunk/rtl/
10	- fix rind mode in 32 bit mode - fix flag update in 32 bit mode for RR instructions - initialize cache tags - added flag to disable ints until after sp load	robfinch	4088d 09h	/rtf65002/trunk/rtl/
5	setting up project	robfinch	4091d 16h	/rtf65002/trunk/rtl/
2	setting up project	robfinch	4091d 16h	/rtf65002/trunk/rtl/