URL https://opencores.org/ocsvn/rtfsimpleuart/rtfsimpleuart/trunk

Subversion Repositories rtfsimpleuart

[/] [rtfsimpleuart/] [trunk/] [rtl/] [verilog/] - Rev 14

Rev	Log message	Author	Age	Path
14	- fix rdxstart clock on baud16x_ce	robfinch	3458d 22h	/rtfsimpleuart/trunk/rtl/verilog/
13	- updated license notice	robfinch	4012d 22h	/rtfsimpleuart/trunk/rtl/verilog/
12	+BaudX8 mode !start frame detector - checks 1->0 transition !frame complectness - frame completes right after center of a frame bit, allows more difference of sender and reciever baud	AlexRayne	4013d 04h	/rtfsimpleuart/trunk/rtl/verilog/
7		robfinch	4809d 04h	/rtfsimpleuart/trunk/rtl/verilog/
6		robfinch	4809d 04h	/rtfsimpleuart/trunk/rtl/verilog/
5		robfinch	4809d 04h	/rtfsimpleuart/trunk/rtl/verilog/
4	initial archive	robfinch	4809d 04h	/rtfsimpleuart/trunk/rtl/verilog/
3	initial archive	robfinch	4809d 04h	/rtfsimpleuart/trunk/rtl/verilog/