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[/] [s1_core/] [trunk/] - Rev 50

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Rev Log message Author Age Path
50 Changed library paths for XST from macrocell to behav. fafa1971 6286d 23h /s1_core/trunk/
49 Now supports 3 versions: S1 Core ME/SE/EE. fafa1971 6294d 00h /s1_core/trunk/
48 Updated with new OpenSPARC 1.4 list fafa1971 6335d 14h /s1_core/trunk/
47 Updated with `define preprocessing for Xilinx XST synthesis fafa1971 6335d 15h /s1_core/trunk/
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6335d 15h /s1_core/trunk/
45 I'm going to remove original OpenSPARC 1.4 files so that I can insert again
the ones with Icarus Verilog preprocessor already applied by update_sparccore
(it seems that Xilinx's XST does NOT support defines at compile time)		 fafa1971 6335d 15h /s1_core/trunk/
44 Embedded `defines into Verilog source since did not find command line option for XST fafa1971 6336d 13h /s1_core/trunk/
43 Added welcome message as a remainder to set paths for tools!=IVerilog fafa1971 6336d 13h /s1_core/trunk/
42 Added support for filelist for Xilinx ISE XST synthesis fafa1971 6336d 13h /s1_core/trunk/
41 Added copy of empty modules upon original SPARC copies fafa1971 6336d 13h /s1_core/trunk/
40 First version of synthesis script for Xilinx ISE XST fafa1971 6336d 13h /s1_core/trunk/
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6336d 13h /s1_core/trunk/
38 Changed to compile (for now) the boot code. fafa1971 6340d 12h /s1_core/trunk/
37 Memory image coming from the new boot.s fafa1971 6340d 12h /s1_core/trunk/
36 Working boot code!!! fafa1971 6340d 12h /s1_core/trunk/
35 Fixed Assembly comments ("//" had to become "!!"). fafa1971 6340d 13h /s1_core/trunk/
34 This file is useless. fafa1971 6349d 21h /s1_core/trunk/
33 Added inclusion of defines.h in boot.s fafa1971 6350d 12h /s1_core/trunk/
32 First version of cutdown boot code for SPARC V9. fafa1971 6350d 12h /s1_core/trunk/
31 Removed list of formerly dirty signals, to improve waveforms readability. fafa1971 6350d 14h /s1_core/trunk/

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