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[/] [s1_core/] [trunk/] - Rev 90

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Rev Log message Author Age Path
90 Added newer files from OpenSPARC T1 1.6 preprocessed with "update_sparccore -ee" fafa1971 5805d 21h /s1_core/trunk/
89 Removed files originated from OpenSPARC T1 Design 1.5 preprocessed with "update_sparccore -me" fafa1971 5805d 21h /s1_core/trunk/
88 After one year found time to translate Giovanni Di Blasi's comments to boot code! fafa1971 5807d 23h /s1_core/trunk/
87 Corrected comment delimiter. fafa1971 5934d 09h /s1_core/trunk/
86 Added 'lain.ux'-style checks for environment vars to be set (I lost data as well!!!). fafa1971 5947d 04h /s1_core/trunk/
85 GREAT synthesis script!!! Performs all bottom-up synthesis without errors. fafa1971 5949d 05h /s1_core/trunk/
84 Again, used module names instead than instance names in bottom-up synthesis approach. fafa1971 5949d 08h /s1_core/trunk/
83 Decreased clock frequency from 250 to 200 MHz. fafa1971 5956d 04h /s1_core/trunk/
82 DC synthesis script modified according to the fabolous manual (RTFM...). fafa1971 5967d 04h /s1_core/trunk/
81 Sorry, I made a mistake in the waveform of the clock! fafa1971 5967d 07h /s1_core/trunk/
80 Hyerarchical report_area. fafa1971 5970d 03h /s1_core/trunk/
79 Relaxed timing, added flatten and hyerarchical report_area. fafa1971 5970d 03h /s1_core/trunk/
78 Relaxed timing and added flatten command. fafa1971 5970d 03h /s1_core/trunk/
77 Now includes comments (in Italian!) fafa1971 6055d 01h /s1_core/trunk/
76 Changed again from DB export to DDC export fafa1971 6070d 00h /s1_core/trunk/
75 Changed preprocessing for DC synthesis fafa1971 6070d 04h /s1_core/trunk/
74 Updated filelists. fafa1971 6070d 04h /s1_core/trunk/
73 New version of scripts for DC and to compile boot code fafa1971 6070d 05h /s1_core/trunk/
72 Modified RAM address from 0x400C0 to 0x4C000 fafa1971 6076d 12h /s1_core/trunk/
71 Added check for S1_ROOT set (suggested by lain.ux) fafa1971 6077d 12h /s1_core/trunk/

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