URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] - Rev 44

Rev	Log message	Author	Age	Path
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6296d 19h	/s1_core/trunk/hdl/rtl/
39	Empty modules for cacheless Simply RISC S1 Core	fafa1971	6296d 19h	/s1_core/trunk/hdl/rtl/
24	Fresh files taken from most recent OpenSPARC 1.4.	fafa1971	6310d 22h	/s1_core/trunk/hdl/rtl/
23	Fresh file taken from the most recent OpenSPARC 1.4.	fafa1971	6310d 22h	/s1_core/trunk/hdl/rtl/
22	Removed files of OpenSPARC 1.3 to later add the 1.4 ones.	fafa1971	6310d 22h	/s1_core/trunk/hdl/rtl/
21	Removed files of OpenSPARC 1.3 to later add version 1.4 ones.	fafa1971	6310d 22h	/s1_core/trunk/hdl/rtl/
20	Removed all the files of OpenSPARC 1.3 to later add the 1.4 ones.	fafa1971	6310d 22h	/s1_core/trunk/hdl/rtl/
19	* empty log message *	fafa1971	6310d 23h	/s1_core/trunk/hdl/rtl/
12	Updated the PCX/CPX fields description with all the info required for debugging.	fafa1971	6371d 18h	/s1_core/trunk/hdl/rtl/
11	Corrected the bug about the packet format, now we are near to perfection...	fafa1971	6371d 21h	/s1_core/trunk/hdl/rtl/
9	First release.	fafa1971	6392d 18h	/s1_core/trunk/hdl/rtl/
6	First version (from OpenSPARC 1.1.3).	fafa1971	6392d 19h	/s1_core/trunk/hdl/rtl/
4	First version.	fafa1971	6392d 19h	/s1_core/trunk/hdl/rtl/