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[/] [s1_core/] [trunk/] [hdl/] [rtl/] - Rev 51

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51 User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables. fafa1971 6254d 22h /s1_core/trunk/hdl/rtl/
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6319d 20h /s1_core/trunk/hdl/rtl/
45 I'm going to remove original OpenSPARC 1.4 files so that I can insert again
the ones with Icarus Verilog preprocessor already applied by update_sparccore
(it seems that Xilinx's XST does NOT support defines at compile time)		 fafa1971 6319d 21h /s1_core/trunk/hdl/rtl/
44 Embedded `defines into Verilog source since did not find command line option for XST fafa1971 6320d 19h /s1_core/trunk/hdl/rtl/
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6320d 19h /s1_core/trunk/hdl/rtl/
24 Fresh files taken from most recent OpenSPARC 1.4. fafa1971 6334d 22h /s1_core/trunk/hdl/rtl/
23 Fresh file taken from the most recent OpenSPARC 1.4. fafa1971 6334d 22h /s1_core/trunk/hdl/rtl/
22 Removed files of OpenSPARC 1.3 to later add the 1.4 ones. fafa1971 6334d 22h /s1_core/trunk/hdl/rtl/
21 Removed files of OpenSPARC 1.3 to later add version 1.4 ones. fafa1971 6334d 22h /s1_core/trunk/hdl/rtl/
20 Removed all the files of OpenSPARC 1.3 to later add the 1.4 ones. fafa1971 6334d 22h /s1_core/trunk/hdl/rtl/
19 *** empty log message *** fafa1971 6334d 22h /s1_core/trunk/hdl/rtl/
12 Updated the PCX/CPX fields description with all the info required for debugging. fafa1971 6395d 17h /s1_core/trunk/hdl/rtl/
11 Corrected the bug about the packet format, now we are near to perfection... fafa1971 6395d 21h /s1_core/trunk/hdl/rtl/
9 First release. fafa1971 6416d 18h /s1_core/trunk/hdl/rtl/
6 First version (from OpenSPARC 1.1.3). fafa1971 6416d 18h /s1_core/trunk/hdl/rtl/
4 First version. fafa1971 6416d 18h /s1_core/trunk/hdl/rtl/

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