URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] - Rev 51

Rev	Log message	Author	Age	Path
51	User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables.	fafa1971	6312d 14h	/s1_core/trunk/hdl/rtl/s1_top/
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6378d 11h	/s1_core/trunk/hdl/rtl/s1_top/
12	Updated the PCX/CPX fields description with all the info required for debugging.	fafa1971	6453d 10h	/s1_core/trunk/hdl/rtl/s1_top/
11	Corrected the bug about the packet format, now we are near to perfection...	fafa1971	6453d 13h	/s1_core/trunk/hdl/rtl/s1_top/
4	First version.	fafa1971	6474d 10h	/s1_core/trunk/hdl/rtl/s1_top/