URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] - Rev 98

Rev	Log message	Author	Age	Path
98	Added stall/resume signals from bridge to SPARC Core.	fafa1971	5679d 19h	/s1_core/trunk/hdl/rtl/s1_top/
73	New version of scripts for DC and to compile boot code	fafa1971	6063d 02h	/s1_core/trunk/hdl/rtl/s1_top/
58	These were only symbolic links to remember where such these things were defined	fafa1971	6125d 17h	/s1_core/trunk/hdl/rtl/s1_top/
51	User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables.	fafa1971	6211d 18h	/s1_core/trunk/hdl/rtl/s1_top/
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6277d 15h	/s1_core/trunk/hdl/rtl/s1_top/
12	Updated the PCX/CPX fields description with all the info required for debugging.	fafa1971	6352d 13h	/s1_core/trunk/hdl/rtl/s1_top/
11	Corrected the bug about the packet format, now we are near to perfection...	fafa1971	6352d 17h	/s1_core/trunk/hdl/rtl/s1_top/
4	First version.	fafa1971	6373d 14h	/s1_core/trunk/hdl/rtl/s1_top/