URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] - Rev 99

Rev	Log message	Author	Age	Path
99	This bridge follows the rules stated in paragraph 6.8 of book "OpenSPARC Internals" in order to stall all the threads while serving a single request.	fafa1971	5686d 08h	/s1_core/trunk/hdl/rtl/s1_top/
98	Added stall/resume signals from bridge to SPARC Core.	fafa1971	5686d 08h	/s1_core/trunk/hdl/rtl/s1_top/
73	New version of scripts for DC and to compile boot code	fafa1971	6069d 16h	/s1_core/trunk/hdl/rtl/s1_top/
58	These were only symbolic links to remember where such these things were defined	fafa1971	6132d 06h	/s1_core/trunk/hdl/rtl/s1_top/
51	User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables.	fafa1971	6218d 07h	/s1_core/trunk/hdl/rtl/s1_top/
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6284d 04h	/s1_core/trunk/hdl/rtl/s1_top/
12	Updated the PCX/CPX fields description with all the info required for debugging.	fafa1971	6359d 03h	/s1_core/trunk/hdl/rtl/s1_top/
11	Corrected the bug about the packet format, now we are near to perfection...	fafa1971	6359d 06h	/s1_core/trunk/hdl/rtl/s1_top/
4	First version.	fafa1971	6380d 03h	/s1_core/trunk/hdl/rtl/s1_top/