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[/] [s1_core/] [trunk/] [tools/] - Rev 47

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Rev Log message Author Age Path
47 Updated with `define preprocessing for Xilinx XST synthesis fafa1971 6286d 05h /s1_core/trunk/tools/
42 Added support for filelist for Xilinx ISE XST synthesis fafa1971 6287d 03h /s1_core/trunk/tools/
41 Added copy of empty modules upon original SPARC copies fafa1971 6287d 04h /s1_core/trunk/tools/
40 First version of synthesis script for Xilinx ISE XST fafa1971 6287d 04h /s1_core/trunk/tools/
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6287d 04h /s1_core/trunk/tools/
38 Changed to compile (for now) the boot code. fafa1971 6291d 03h /s1_core/trunk/tools/
31 Removed list of formerly dirty signals, to improve waveforms readability. fafa1971 6301d 05h /s1_core/trunk/tools/
27 Added "tee" to see output both on screen and saved in the logfile. fafa1971 6301d 06h /s1_core/trunk/tools/
26 Added "tee" commands to see the output both on screen and saved on logfile. fafa1971 6301d 06h /s1_core/trunk/tools/
16 Added the 3 new defines to make the design:
- synthesizable for FPGA
- single-threaded
- without the cryptographic SPU unit		 fafa1971 6301d 17h /s1_core/trunk/tools/
15 Removed the remove of CVS subdirs... fafa1971 6301d 17h /s1_core/trunk/tools/
13 Added first version of small tool to reverse engineer the boot code used by the T1. fafa1971 6361d 11h /s1_core/trunk/tools/
12 Updated the PCX/CPX fields description with all the info required for debugging. fafa1971 6362d 02h /s1_core/trunk/tools/
11 Corrected the bug about the packet format, now we are near to perfection... fafa1971 6362d 05h /s1_core/trunk/tools/
10 First version. fafa1971 6383d 03h /s1_core/trunk/tools/
8 First release. fafa1971 6383d 03h /s1_core/trunk/tools/
7 First version. fafa1971 6383d 03h /s1_core/trunk/tools/

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