URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [tools/] [src/] - Rev 72

Rev	Log message	Author	Age	Path
72	Modified RAM address from 0x400C0 to 0x4C000	fafa1971	6077d 06h	/s1_core/trunk/tools/src/
69	Now contains also the other file	fafa1971	6085d 15h	/s1_core/trunk/tools/src/
68	Merged with the DC setup file	fafa1971	6085d 16h	/s1_core/trunk/tools/src/
66	Modified to use XG syntax	fafa1971	6087d 16h	/s1_core/trunk/tools/src/
65	Version with undisclosed library names	fafa1971	6087d 16h	/s1_core/trunk/tools/src/
64	Initial version B C C Initial versioNCVS: ----------------------------------------------------------------------	fafa1971	6087d 16h	/s1_core/trunk/tools/src/
63	* empty log message *	fafa1971	6087d 16h	/s1_core/trunk/tools/src/
60	Now supports also Virtex5 devices	fafa1971	6133d 14h	/s1_core/trunk/tools/src/
40	First version of synthesis script for Xilinx ISE XST	fafa1971	6285d 12h	/s1_core/trunk/tools/src/
39	Empty modules for cacheless Simply RISC S1 Core	fafa1971	6285d 12h	/s1_core/trunk/tools/src/
31	Removed list of formerly dirty signals, to improve waveforms readability.	fafa1971	6299d 13h	/s1_core/trunk/tools/src/
7	First version.	fafa1971	6381d 11h	/s1_core/trunk/tools/src/