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[/] [s1_core/] [trunk/] [tools/] [src/] - Rev 83

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Rev Log message Author Age Path
83 Decreased clock frequency from 250 to 200 MHz. fafa1971 6051d 02h /s1_core/trunk/tools/src/
82 DC synthesis script modified according to the fabolous manual (RTFM...). fafa1971 6062d 02h /s1_core/trunk/tools/src/
81 Sorry, I made a mistake in the waveform of the clock! fafa1971 6062d 06h /s1_core/trunk/tools/src/
80 Hyerarchical report_area. fafa1971 6065d 02h /s1_core/trunk/tools/src/
78 Relaxed timing and added flatten command. fafa1971 6065d 02h /s1_core/trunk/tools/src/
76 Changed again from DB export to DDC export fafa1971 6164d 23h /s1_core/trunk/tools/src/
73 New version of scripts for DC and to compile boot code fafa1971 6165d 03h /s1_core/trunk/tools/src/
72 Modified RAM address from 0x400C0 to 0x4C000 fafa1971 6171d 10h /s1_core/trunk/tools/src/
69 Now contains also the other file fafa1971 6179d 20h /s1_core/trunk/tools/src/
68 Merged with the DC setup file fafa1971 6179d 20h /s1_core/trunk/tools/src/
66 Modified to use XG syntax fafa1971 6181d 20h /s1_core/trunk/tools/src/
65 Version with undisclosed library names fafa1971 6181d 20h /s1_core/trunk/tools/src/
64 Initial version
B
C
C
Initial versioNCVS: ----------------------------------------------------------------------		 fafa1971 6181d 20h /s1_core/trunk/tools/src/
63 *** empty log message *** fafa1971 6181d 20h /s1_core/trunk/tools/src/
60 Now supports also Virtex5 devices fafa1971 6227d 18h /s1_core/trunk/tools/src/
40 First version of synthesis script for Xilinx ISE XST fafa1971 6379d 16h /s1_core/trunk/tools/src/
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6379d 16h /s1_core/trunk/tools/src/
31 Removed list of formerly dirty signals, to improve waveforms readability. fafa1971 6393d 17h /s1_core/trunk/tools/src/
7 First version. fafa1971 6475d 15h /s1_core/trunk/tools/src/

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