URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] - Rev 12

Rev	Log message	Author	Age	Path
12	The UART and PWM audio now work. This includes the changes to make that happen, as well as the source code for some UART and PWM demo programs.	dgisselq	3070d 12h	/s6soc/trunk/rtl/
11	Runs on hardware now! Added proper pinouts, pipelined wishbone command interface sufficient for loading the flash, a loader to load the flash, and verified that they work.	dgisselq	3071d 10h	/s6soc/trunk/rtl/
8	First pseudo-running version. The alternate configuration (not the main one) has been initially tested. wbregs works for reading/writing registers, so it is now possible to test the peripherals.	dgisselq	3076d 10h	/s6soc/trunk/rtl/
7	Created/added an initial specification. Updated/corrected several copywrite notices.	dgisselq	3077d 01h	/s6soc/trunk/rtl/
5	These two are my first attempt(s) at a secondary project file, one that can run as an alternate to the main file but that gives more access to the hardware, such as programming access to the flash.	dgisselq	3097d 20h	/s6soc/trunk/rtl/
4	Lots of updates, as part of actually making this work on hardware. Not there yet, so this is still pre-alpha.	dgisselq	3097d 20h	/s6soc/trunk/rtl/
3	Updated date.	dgisselq	3097d 20h	/s6soc/trunk/rtl/
2	The initial check in--all the files that will make this SoC work.	dgisselq	3108d 15h	/s6soc/trunk/rtl/