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[/] [s6soc/] [trunk/] [sw/] [host/] - Rev 49

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Rev Log message Author Age Path
48 Added missing sw/host and sw/zipos files dgisselq 2757d 13h /s6soc/trunk/sw/host/
45 S6SoC 8-bit support dgisselq 2757d 13h /s6soc/trunk/sw/host/
38 Updated the documentation. dgisselq 3053d 04h /s6soc/trunk/sw/host/
26 Modified to be able to handle different load from virtual addresses. This
enables the bootloader capability.		 dgisselq 3060d 13h /s6soc/trunk/sw/host/
19 Addition of dumpuart.cpp to dump the UART transactions to a FILE (method of
debugging the board). FLASHDRVR and ZIPLOAD were also updated to handle
loading ELF files where the code is longer than a single block.		 dgisselq 3064d 12h /s6soc/trunk/sw/host/
14 Modified the loader so that it will load even if there are RAM variables
in the load, just as long as they aren't anything but zero. (The startup code,
however, doesn't clear memory to match--so be sure to initialize all variables.)		 dgisselq 3070d 06h /s6soc/trunk/sw/host/
12 The UART and PWM audio now work. This includes the changes to make that
happen, as well as the source code for some UART and PWM demo programs.		 dgisselq 3071d 04h /s6soc/trunk/sw/host/
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.		 dgisselq 3072d 02h /s6soc/trunk/sw/host/
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.		 dgisselq 3077d 02h /s6soc/trunk/sw/host/

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