OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] - Rev 129

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4924d 04h /sdhc-sc-core/
128 Sim: Support for psl files added. rkastl 4924d 04h /sdhc-sc-core/
127 Thesis: Restructured SDHC chapter. rkastl 4924d 04h /sdhc-sc-core/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4924d 04h /sdhc-sc-core/
125 Write works in simulation rkastl 4924d 04h /sdhc-sc-core/
124 Write: SdClk is disabled, if no data is available. rkastl 4924d 04h /sdhc-sc-core/
123 Write: Must be able to halt SdClk, rest is done. rkastl 4924d 04h /sdhc-sc-core/
122 SdController: Initial read support rkastl 4924d 07h /sdhc-sc-core/
121 SdWbSlave inserted into SdTop. SdController does not use it yet. rkastl 4924d 08h /sdhc-sc-core/
120 SdWbSlave: ClassicRead and ClassicWrite work rkastl 4924d 08h /sdhc-sc-core/
119 SdWb: Synchronization of operation to SdController done, but needs
testing.		 rkastl 4924d 08h /sdhc-sc-core/
118 EdgeDetector added. rkastl 4924d 08h /sdhc-sc-core/
117 Removed unused units. rkastl 4924d 08h /sdhc-sc-core/
116 Wishbone interface for sd core started rkastl 4924d 08h /sdhc-sc-core/
115 WbSlave: New header. rkastl 4924d 08h /sdhc-sc-core/
114 Read works with model too. rkastl 4924d 08h /sdhc-sc-core/
113 Read with single block works on cards, but not in simulation. SdData.sv
sends data with one "XXXX" cycle right before the crc.		 rkastl 4924d 08h /sdhc-sc-core/
112 Save wide mode with out gHighSpeedMode = true rkastl 4924d 08h /sdhc-sc-core/
111 Sclk moved to neg. edge -> setup and hold times for fast mode are easier
to reach. (only micro sd does not work in fast mode).		 rkastl 4924d 08h /sdhc-sc-core/
110 All except microsd work in highspeed mode. rkastl 4924d 08h /sdhc-sc-core/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.