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[/] [sdhc-sc-core/] - Rev 161

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Rev Log message Author Age Path
161 Verification:
CardModel: Check CRC on received data		 rkastl 4911d 12h /sdhc-sc-core/
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4911d 12h /sdhc-sc-core/
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4911d 12h /sdhc-sc-core/
158 Verification:
Work on Checking
Functional coverage		 rkastl 4911d 12h /sdhc-sc-core/
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4911d 12h /sdhc-sc-core/
156 SdVerification:
+ Split a SdCoreTransaction into multiple WbTransactions: Proof
of Concept with a ReadSingleBlock-Transaction
+ Finish after certain amount of time and present simulation
result		 rkastl 4911d 12h /sdhc-sc-core/
155 SdVerification:
continue to work on it, not done.		 rkastl 4911d 12h /sdhc-sc-core/
154 SdVerification:
- started sending with mailboxes		 rkastl 4911d 12h /sdhc-sc-core/
153 SdVerification:
further development, not done by far		 rkastl 4911d 12h /sdhc-sc-core/
152 SdClockMaster:
Generate InStrobe so that it the sd bus gets captured on the
rising edge of the clock in high speed mode		 rkastl 4911d 12h /sdhc-sc-core/
151 Verification:
+ redesign: not functional yet		 rkastl 4911d 12h /sdhc-sc-core/
150 Testbed:
+ Simulation made possible
+ Write works
- Sometimes the alignment in the block is not right		 rkastl 4911d 12h /sdhc-sc-core/
149 SdBFM:
+ mailbox mode		 rkastl 4911d 12h /sdhc-sc-core/
148 SdVerification:
+ CardModel: Execution thread which starts initialization and
then receives token and parses them.

TbdSd:
+ Added SdWbSdSynchronization.		 rkastl 4911d 12h /sdhc-sc-core/
147 Sd-Core:
+ Added checking of Busy signal after write		 rkastl 4911d 12h /sdhc-sc-core/
146 SdClockMaster:
+ fixed output of data at negedge of sclk in high speed mode		 rkastl 4911d 12h /sdhc-sc-core/
145 Verification:
+ SdCardModel and SdBFM seperated		 rkastl 4911d 12h /sdhc-sc-core/
144 Simulation files for tbTbdSd created.

tbTbdSd is not done and TestWbMaster seems to be lost.		 rkastl 4911d 12h /sdhc-sc-core/
143 Ignore pattern:
+ work
+ modelsim.ini
+ vsim.wlf
+ transcript
+ cycloneii and altera_mf generated library folders		 rkastl 4911d 12h /sdhc-sc-core/
142 Thesis: PDF added to .gitignore rkastl 4911d 12h /sdhc-sc-core/

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