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[/] [sdhc-sc-core/] - Rev 170

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Rev Log message Author Age Path
170 License rewritten to BSD rkastl 4890d 18h /sdhc-sc-core/
169 +sdc file for timing analysis rkastl 4890d 18h /sdhc-sc-core/
168 TbdSd synthesis script reaches timing constraints. rkastl 4890d 18h /sdhc-sc-core/
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4890d 18h /sdhc-sc-core/
166 tbTbdSd: fixed rkastl 4890d 18h /sdhc-sc-core/
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4890d 18h /sdhc-sc-core/
164 Headers updated (LGPL, consistent format) rkastl 4890d 18h /sdhc-sc-core/
163 Header-Skript supports writing to file and infile replacement. rkastl 4890d 18h /sdhc-sc-core/
162 Script for generating headers created. rkastl 4890d 18h /sdhc-sc-core/
161 Verification:
CardModel: Check CRC on received data		 rkastl 4890d 18h /sdhc-sc-core/
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4890d 18h /sdhc-sc-core/
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4890d 18h /sdhc-sc-core/
158 Verification:
Work on Checking
Functional coverage		 rkastl 4890d 18h /sdhc-sc-core/
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4890d 18h /sdhc-sc-core/
156 SdVerification:
+ Split a SdCoreTransaction into multiple WbTransactions: Proof
of Concept with a ReadSingleBlock-Transaction
+ Finish after certain amount of time and present simulation
result		 rkastl 4890d 18h /sdhc-sc-core/
155 SdVerification:
continue to work on it, not done.		 rkastl 4890d 18h /sdhc-sc-core/
154 SdVerification:
- started sending with mailboxes		 rkastl 4890d 18h /sdhc-sc-core/
153 SdVerification:
further development, not done by far		 rkastl 4890d 18h /sdhc-sc-core/
152 SdClockMaster:
Generate InStrobe so that it the sd bus gets captured on the
rising edge of the clock in high speed mode		 rkastl 4890d 18h /sdhc-sc-core/
151 Verification:
+ redesign: not functional yet		 rkastl 4890d 18h /sdhc-sc-core/

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