URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] - Rev 79

Rev	Log message	Author	Age	Path
79	Rs232Tx: added to TbdSd TimeoutGenerator: written	rkastl	4928d 22h	/sdhc-sc-core/
78	Rs232Tx: implemented, but not tested	rkastl	4928d 22h	/sdhc-sc-core/
77	refs #25, synthesis works again	rkastl	4928d 22h	/sdhc-sc-core/
76	SdCmd: ioCmd, output registered, fixes #26	rkastl	4928d 22h	/sdhc-sc-core/
75	Transfer to SbX, ref #17	rkastl	4928d 22h	/sdhc-sc-core/
74	Testbed: All pins, refs #17	rkastl	4928d 22h	/sdhc-sc-core/
73	Testbed: Pins.tcl into TbdSdsyn.tcl, refs #17	rkastl	4928d 22h	/sdhc-sc-core/
72	TbdSdsyn: +Pins.tcl, refs #17	rkastl	4928d 22h	/sdhc-sc-core/
71	Testbed added to synthesis builds	rkastl	4928d 22h	/sdhc-sc-core/
70	Testbed: Status leds	rkastl	4928d 22h	/sdhc-sc-core/
69	TbdSd synthesis	rkastl	4928d 22h	/sdhc-sc-core/
68	Testbed for SD-CORE, refs #17	rkastl	4928d 22h	/sdhc-sc-core/
67	IP added	rkastl	4928d 22h	/sdhc-sc-core/
66	SdTop: Synthesis works	rkastl	4928d 22h	/sdhc-sc-core/
65	SdTop: all sd pins	rkastl	4928d 22h	/sdhc-sc-core/
64	SdCommand: Gemeinsamen crc7 verwendet SDController: + voltage checks, refs #15	rkastl	4928d 22h	/sdhc-sc-core/
63	SdController: basic init complete	rkastl	4928d 22h	/sdhc-sc-core/
62	R2 implemented in complete stack, refs #15.	rkastl	4928d 22h	/sdhc-sc-core/
61	Crc: Additional test case	rkastl	4928d 22h	/sdhc-sc-core/
60	Receiving a response to ACMD41 works (including busy, but voltage is not checked), refs #15.	rkastl	4928d 22h	/sdhc-sc-core/