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[/] [sdhc-sc-core/] [trunk/] [src/] - Rev 180

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Rev Log message Author Age Path
180 Moved WbClkDomain to its own unit.
Refs #60.		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
179 Fixing build:
Added library generation to Makefile.		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
178 Fixed regression:
Testbenches did not support synchronous reset.		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
177 Split SdTop into SdClkDomain and SdTop. Refs #60. rkastl 4891d 06h /sdhc-sc-core/trunk/src/
176 Thesis:
Conclusion

Fixes #53,#61.		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
171 Worked on wishbone part of thesis.

Refs #37.
Refs #39.		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
170 License rewritten to BSD rkastl 4891d 06h /sdhc-sc-core/trunk/src/
169 +sdc file for timing analysis rkastl 4891d 06h /sdhc-sc-core/trunk/src/
168 TbdSd synthesis script reaches timing constraints. rkastl 4891d 06h /sdhc-sc-core/trunk/src/
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
166 tbTbdSd: fixed rkastl 4891d 06h /sdhc-sc-core/trunk/src/
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4891d 06h /sdhc-sc-core/trunk/src/
164 Headers updated (LGPL, consistent format) rkastl 4891d 06h /sdhc-sc-core/trunk/src/
161 Verification:
CardModel: Check CRC on received data		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
158 Verification:
Work on Checking
Functional coverage		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
156 SdVerification:
+ Split a SdCoreTransaction into multiple WbTransactions: Proof
of Concept with a ReadSingleBlock-Transaction
+ Finish after certain amount of time and present simulation
result		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/
155 SdVerification:
continue to work on it, not done.		 rkastl 4891d 06h /sdhc-sc-core/trunk/src/

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