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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] - Rev 137

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Rev Log message Author Age Path
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)		 rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
135 Multiple-Inclusion-Protection to SystemVerilog files added
Stops using relative paths in `includes. instead +incdir has to be used.		 rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
134 SdData: Further refactoring. rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
133 SdData: Further refactoring rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
132 SdData: Refactoring, not done.
Testbench works again, but does not really test anything.		 rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
130 SdClockMaster: Formal verification rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
125 Write works in simulation rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
124 Write: SdClk is disabled, if no data is available. rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
123 Write: Must be able to halt SdClk, rest is done. rkastl 4924d 04h /sdhc-sc-core/trunk/src/grpSd/
122 SdController: Initial read support rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/
121 SdWbSlave inserted into SdTop. SdController does not use it yet. rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/
120 SdWbSlave: ClassicRead and ClassicWrite work rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/
119 SdWb: Synchronization of operation to SdController done, but needs
testing.		 rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/
117 Removed unused units. rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/
116 Wishbone interface for sd core started rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/
114 Read works with model too. rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/
113 Read with single block works on cards, but not in simulation. SdData.sv
sends data with one "XXXX" cycle right before the crc.		 rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/
112 Save wide mode with out gHighSpeedMode = true rkastl 4924d 07h /sdhc-sc-core/trunk/src/grpSd/

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