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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdClockMaster/] [src/] - Rev 185

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Rev Log message Author Age Path
185 Restructuring as source repository: Moved sources out of src subdirectory. rkastl 4920d 12h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
170 License rewritten to BSD rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
164 Headers updated (LGPL, consistent format) rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
152 SdClockMaster:
Generate InStrobe so that it the sd bus gets captured on the
rising edge of the clock in high speed mode		 rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
150 Testbed:
+ Simulation made possible
+ Write works
- Sometimes the alignment in the block is not right		 rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
146 SdClockMaster:
+ fixed output of data at negedge of sclk in high speed mode		 rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
130 SdClockMaster: Formal verification rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
125 Write works in simulation rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
124 Write: SdClk is disabled, if no data is available. rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/
121 SdWbSlave inserted into SdTop. SdController does not use it yet. rkastl 4923d 10h /sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/

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