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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdData/] - Rev 130

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126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4942d 09h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
124 Write: SdClk is disabled, if no data is available. rkastl 4942d 09h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
123 Write: Must be able to halt SdClk, rest is done. rkastl 4942d 09h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
113 Read with single block works on cards, but not in simulation. SdData.sv
sends data with one "XXXX" cycle right before the crc.		 rkastl 4942d 12h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
111 Sclk moved to neg. edge -> setup and hold times for fast mode are easier
to reach. (only micro sd does not work in fast mode).		 rkastl 4942d 12h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
110 All except microsd work in highspeed mode. rkastl 4942d 12h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
109 Added a data ram. rkastl 4942d 12h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
105 Changing speed works! refs #33 rkastl 4942d 13h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
103 SdController: Checking speed works rkastl 4942d 13h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
101 Receiving response to ACMD51 works including data, refs #33. rkastl 4942d 13h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
100 SdController: Receiving data after ACMD51, but CRC is wrong rkastl 4942d 13h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
95 SdController: entity and architecture split, all outputs registered
SdCardModel: Delay between response and next command added
SdData: Busy checking

refs #33		 rkastl 4942d 13h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
93 Don´t run a full synthesis for SdData alone. It won´t fit. rkastl 4942d 13h /sdhc-sc-core/trunk/src/grpSd/unitSdData/
92 SdData: Sending in standard and wide mode (incl. simple not automated
testbench and synthesis), refs #31.		 rkastl 4942d 13h /sdhc-sc-core/trunk/src/grpSd/unitSdData/

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