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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdVerificationTestbench/] - Rev 177

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177 Split SdTop into SdClkDomain and SdTop. Refs #60. rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
176 Thesis:
Conclusion

Fixes #53,#61.		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
170 License rewritten to BSD rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
164 Headers updated (LGPL, consistent format) rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
161 Verification:
CardModel: Check CRC on received data		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
158 Verification:
Work on Checking
Functional coverage		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
156 SdVerification:
+ Split a SdCoreTransaction into multiple WbTransactions: Proof
of Concept with a ReadSingleBlock-Transaction
+ Finish after certain amount of time and present simulation
result		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
153 SdVerification:
further development, not done by far		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
151 Verification:
+ redesign: not functional yet		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
150 Testbed:
+ Simulation made possible
+ Write works
- Sometimes the alignment in the block is not right		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
148 SdVerification:
+ CardModel: Execution thread which starts initialization and
then receives token and parses them.

TbdSd:
+ Added SdWbSdSynchronization.		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
147 Sd-Core:
+ Added checking of Busy signal after write		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
145 Verification:
+ SdCardModel and SdBFM seperated		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
135 Multiple-Inclusion-Protection to SystemVerilog files added
Stops using relative paths in `includes. instead +incdir has to be used.		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/
125 Write works in simulation rkastl 4921d 00h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/

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