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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdVerificationTestbench/] [sim/] - Rev 158

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Rev Log message Author Age Path
158 Verification:
Work on Checking
Functional coverage		 rkastl 4962d 14h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4962d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
153 SdVerification:
further development, not done by far		 rkastl 4962d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
147 Sd-Core:
+ Added checking of Busy signal after write		 rkastl 4962d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)		 rkastl 4962d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4962d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
125 Write works in simulation rkastl 4962d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
124 Write: SdClk is disabled, if no data is available. rkastl 4962d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
123 Write: Must be able to halt SdClk, rest is done. rkastl 4962d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
122 SdController: Initial read support rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
113 Read with single block works on cards, but not in simulation. SdData.sv
sends data with one "XXXX" cycle right before the crc.		 rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
111 Sclk moved to neg. edge -> setup and hold times for fast mode are easier
to reach. (only micro sd does not work in fast mode).		 rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
109 Added a data ram. rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
108 Added a ram to the testbed rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
106 Fixes #29: All cards respond, but they do not all work. rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
105 Changing speed works! refs #33 rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
101 Receiving response to ACMD51 works including data, refs #33. rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
100 SdController: Receiving data after ACMD51, but CRC is wrong rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
94 CmdTimeout (8 Clocks) added, SdData inserted into top, refs #31 rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/
89 Fixes #27, R3 uses '1111111' as CRC. rkastl 4962d 18h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/

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