OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdWbSlave/] - Rev 185

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
185 Restructuring as source repository: Moved sources out of src subdirectory. rkastl 4920d 12h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
184 Removed WbSlave shell (refs #69)
Moved verification sources to grpSdVerification (fixes #70)		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
171 Worked on wishbone part of thesis.

Refs #37.
Refs #39.		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
170 License rewritten to BSD rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
164 Headers updated (LGPL, consistent format) rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
158 Verification:
Work on Checking
Functional coverage		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
156 SdVerification:
+ Split a SdCoreTransaction into multiple WbTransactions: Proof
of Concept with a ReadSingleBlock-Transaction
+ Finish after certain amount of time and present simulation
result		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
155 SdVerification:
continue to work on it, not done.		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
153 SdVerification:
further development, not done by far		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
151 Verification:
+ redesign: not functional yet		 rkastl 4923d 06h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
139 Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in
the complete verification environment anyway.		 rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
135 Multiple-Inclusion-Protection to SystemVerilog files added
Stops using relative paths in `includes. instead +incdir has to be used.		 rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
123 Write: Must be able to halt SdClk, rest is done. rkastl 4923d 07h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
122 SdController: Initial read support rkastl 4923d 10h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
120 SdWbSlave: ClassicRead and ClassicWrite work rkastl 4923d 10h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
119 SdWb: Synchronization of operation to SdController done, but needs
testing.		 rkastl 4923d 10h /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.