URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdWbSlave/] - Rev 144

Rev	Log message	Author	Age	Path
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4933d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4933d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4933d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4933d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
122	SdController: Initial read support	rkastl	4933d 23h	/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
120	SdWbSlave: ClassicRead and ClassicWrite work	rkastl	4933d 23h	/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
119	SdWb: Synchronization of operation to SdController done, but needs testing.	rkastl	4933d 23h	/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/
116	Wishbone interface for sd core started	rkastl	4933d 23h	/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/