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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitTbdSd/] - Rev 176

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170 License rewritten to BSD rkastl 4921d 03h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
169 +sdc file for timing analysis rkastl 4921d 03h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
168 TbdSd synthesis script reaches timing constraints. rkastl 4921d 03h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4921d 03h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
166 tbTbdSd: fixed rkastl 4921d 03h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4921d 04h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
164 Headers updated (LGPL, consistent format) rkastl 4921d 04h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
151 Verification:
+ redesign: not functional yet		 rkastl 4921d 04h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
150 Testbed:
+ Simulation made possible
+ Write works
- Sometimes the alignment in the block is not right		 rkastl 4921d 04h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
148 SdVerification:
+ CardModel: Execution thread which starts initialization and
then receives token and parses them.

TbdSd:
+ Added SdWbSdSynchronization.		 rkastl 4921d 04h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
144 Simulation files for tbTbdSd created.

tbTbdSd is not done and TestWbMaster seems to be lost.		 rkastl 4921d 04h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)		 rkastl 4921d 04h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4921d 04h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
122 SdController: Initial read support rkastl 4921d 07h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
121 SdWbSlave inserted into SdTop. SdController does not use it yet. rkastl 4921d 07h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
113 Read with single block works on cards, but not in simulation. SdData.sv
sends data with one "XXXX" cycle right before the crc.		 rkastl 4921d 07h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
111 Sclk moved to neg. edge -> setup and hold times for fast mode are easier
to reach. (only micro sd does not work in fast mode).		 rkastl 4921d 07h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
110 All except microsd work in highspeed mode. rkastl 4921d 07h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
109 Added a data ram. rkastl 4921d 07h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/
108 Added a ram to the testbed rkastl 4921d 07h /sdhc-sc-core/trunk/src/grpSd/unitTbdSd/

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