URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitTbdSd/] [syn/] - Rev 181

Rev	Log message	Author	Age	Path
170	License rewritten to BSD	rkastl	4919d 01h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
169	+sdc file for timing analysis	rkastl	4919d 01h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
168	TbdSd synthesis script reaches timing constraints.	rkastl	4919d 01h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
164	Headers updated (LGPL, consistent format)	rkastl	4919d 01h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4919d 01h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
106	Fixes #29: All cards respond, but they do not all work.	rkastl	4919d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
85	Synthese: TbdSd refactored to enable sharing. Sim: SdVerificationTestbench to new tcl script ported SdController: TimeoutGenerator added, refs #27	rkastl	4919d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
79	Rs232Tx: added to TbdSd TimeoutGenerator: written	rkastl	4919d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
75	Transfer to SbX, ref #17	rkastl	4919d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
74	Testbed: All pins, refs #17	rkastl	4919d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
73	Testbed: Pins.tcl into TbdSdsyn.tcl, refs #17	rkastl	4919d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
72	TbdSdsyn: +Pins.tcl, refs #17	rkastl	4919d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/
69	TbdSd synthesis	rkastl	4919d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/syn/