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[/] [sdr_ctrl/] - Rev 10

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Rev Log message Author Age Path
10 Waveform files are added into SVN dinesha 4674d 07h /sdr_ctrl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4675d 06h /sdr_ctrl/
8 test bench files are added into SVN dinesha 4675d 06h /sdr_ctrl/
7 SDRAM Memory Models are added into SVN dinesha 4675d 06h /sdr_ctrl/
6 Golden Log files are added into SVN dinesha 4675d 06h /sdr_ctrl/
5 Run files are updated into SVN dinesha 4675d 06h /sdr_ctrl/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4676d 04h /sdr_ctrl/
3 SDRAM controller core files are checked in dinesha 4682d 14h /sdr_ctrl/
2 dinesha 4685d 06h /sdr_ctrl/
1 The project and the structure was created root 4689d 06h /sdr_ctrl/

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