URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 13

Rev	Log message	Author	Age	Path
13	column bit are made progrmmable	dinesha	4670d 23h	/sdr_ctrl/
12	Column Bits are made programmable	dinesha	4670d 23h	/sdr_ctrl/
11	SDRAM Specification document added into SVN	dinesha	4674d 00h	/sdr_ctrl/
10	Waveform files are added into SVN	dinesha	4674d 00h	/sdr_ctrl/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4675d 00h	/sdr_ctrl/
8	test bench files are added into SVN	dinesha	4675d 00h	/sdr_ctrl/
7	SDRAM Memory Models are added into SVN	dinesha	4675d 00h	/sdr_ctrl/
6	Golden Log files are added into SVN	dinesha	4675d 00h	/sdr_ctrl/
5	Run files are updated into SVN	dinesha	4675d 00h	/sdr_ctrl/
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4675d 21h	/sdr_ctrl/
3	SDRAM controller core files are checked in	dinesha	4682d 08h	/sdr_ctrl/
2		dinesha	4685d 00h	/sdr_ctrl/
1	The project and the structure was created	root	4688d 23h	/sdr_ctrl/