URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 46

Rev	Log message	Author	Age	Path
46	test bench upgrade + rtl cleanup	dinesha	4624d 07h	/sdr_ctrl/trunk/rtl/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4624d 11h	/sdr_ctrl/trunk/rtl/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4626d 09h	/sdr_ctrl/trunk/rtl/
42	Bug fix in read access is fixed	dinesha	4626d 11h	/sdr_ctrl/trunk/rtl/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4627d 06h	/sdr_ctrl/trunk/rtl/
38	Port Name clean up	dinesha	4628d 11h	/sdr_ctrl/trunk/rtl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4628d 13h	/sdr_ctrl/trunk/rtl/
36	Clean up	dinesha	4629d 04h	/sdr_ctrl/trunk/rtl/
33	clean up	dinesha	4629d 06h	/sdr_ctrl/trunk/rtl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4631d 05h	/sdr_ctrl/trunk/rtl/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4633d 09h	/sdr_ctrl/trunk/rtl/
16	8 Bit SDRAM Support is added	dinesha	4635d 04h	/sdr_ctrl/trunk/rtl/
15	Port cleanup	dinesha	4638d 04h	/sdr_ctrl/trunk/rtl/
13	column bit are made progrmmable	dinesha	4638d 05h	/sdr_ctrl/trunk/rtl/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4642d 05h	/sdr_ctrl/trunk/rtl/
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4643d 03h	/sdr_ctrl/trunk/rtl/
3	SDRAM controller core files are checked in	dinesha	4649d 13h	/sdr_ctrl/trunk/rtl/
2		dinesha	4652d 05h	/sdr_ctrl/trunk/rtl/