URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 45

Rev	Log message	Author	Age	Path
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4587d 19h	/sdr_ctrl/trunk/rtl/core/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4589d 17h	/sdr_ctrl/trunk/rtl/core/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4591d 20h	/sdr_ctrl/trunk/rtl/core/
36	Clean up	dinesha	4592d 11h	/sdr_ctrl/trunk/rtl/core/
33	clean up	dinesha	4592d 13h	/sdr_ctrl/trunk/rtl/core/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4594d 12h	/sdr_ctrl/trunk/rtl/core/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4596d 16h	/sdr_ctrl/trunk/rtl/core/
16	8 Bit SDRAM Support is added	dinesha	4598d 11h	/sdr_ctrl/trunk/rtl/core/
15	Port cleanup	dinesha	4601d 12h	/sdr_ctrl/trunk/rtl/core/
13	column bit are made progrmmable	dinesha	4601d 12h	/sdr_ctrl/trunk/rtl/core/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4605d 13h	/sdr_ctrl/trunk/rtl/core/
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4606d 10h	/sdr_ctrl/trunk/rtl/core/
3	SDRAM controller core files are checked in	dinesha	4612d 20h	/sdr_ctrl/trunk/rtl/core/