URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] - Rev 67

Rev	Log message	Author	Age	Path
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4390d 04h	/sdr_ctrl/trunk/rtl/top/
60	warning cleanup	dinesha	4509d 12h	/sdr_ctrl/trunk/rtl/top/
55	FPGA Synthesis timing optimisation	dinesha	4510d 04h	/sdr_ctrl/trunk/rtl/top/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4517d 05h	/sdr_ctrl/trunk/rtl/top/
46	test bench upgrade + rtl cleanup	dinesha	4519d 06h	/sdr_ctrl/trunk/rtl/top/
38	Port Name clean up	dinesha	4523d 10h	/sdr_ctrl/trunk/rtl/top/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4523d 11h	/sdr_ctrl/trunk/rtl/top/
33	clean up	dinesha	4524d 04h	/sdr_ctrl/trunk/rtl/top/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4526d 03h	/sdr_ctrl/trunk/rtl/top/