URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] - Rev 72

Rev	Log message	Author	Age	Path
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4053d 21h	/sdr_ctrl/trunk/rtl/wb2sdrc/
59	Control path request and data are register now for better FPGA timing	dinesha	4491d 04h	/sdr_ctrl/trunk/rtl/wb2sdrc/
55	FPGA Synthesis timing optimisation	dinesha	4491d 19h	/sdr_ctrl/trunk/rtl/wb2sdrc/
42	Bug fix in read access is fixed	dinesha	4503d 02h	/sdr_ctrl/trunk/rtl/wb2sdrc/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4503d 20h	/sdr_ctrl/trunk/rtl/wb2sdrc/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4505d 03h	/sdr_ctrl/trunk/rtl/wb2sdrc/
33	clean up	dinesha	4505d 20h	/sdr_ctrl/trunk/rtl/wb2sdrc/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4507d 19h	/sdr_ctrl/trunk/rtl/wb2sdrc/