URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 34

Rev	Log message	Author	Age	Path
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4508d 10h	/sdr_ctrl/trunk/verif/tb/
25	tb.sv is renamed as tb_top	dinesha	4509d 08h	/sdr_ctrl/trunk/verif/tb/
24	Clean Up	dinesha	4509d 08h	/sdr_ctrl/trunk/verif/tb/
22	Pad sdram clock added	dinesha	4510d 14h	/sdr_ctrl/trunk/verif/tb/
18	8 Bit SDRAM Support is added	dinesha	4512d 08h	/sdr_ctrl/trunk/verif/tb/
14	Unnecessary device config are removed	dinesha	4515d 09h	/sdr_ctrl/trunk/verif/tb/
12	Column Bits are made programmable	dinesha	4515d 10h	/sdr_ctrl/trunk/verif/tb/
8	test bench files are added into SVN	dinesha	4519d 10h	/sdr_ctrl/trunk/verif/tb/
2		dinesha	4529d 10h	/sdr_ctrl/trunk/verif/tb/