URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 38

Rev	Log message	Author	Age	Path
38	Port Name clean up	dinesha	4628d 18h	/sdr_ctrl/trunk/verif/tb/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4628d 19h	/sdr_ctrl/trunk/verif/tb/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4631d 12h	/sdr_ctrl/trunk/verif/tb/
25	tb.sv is renamed as tb_top	dinesha	4632d 10h	/sdr_ctrl/trunk/verif/tb/
24	Clean Up	dinesha	4632d 10h	/sdr_ctrl/trunk/verif/tb/
22	Pad sdram clock added	dinesha	4633d 15h	/sdr_ctrl/trunk/verif/tb/
18	8 Bit SDRAM Support is added	dinesha	4635d 10h	/sdr_ctrl/trunk/verif/tb/
14	Unnecessary device config are removed	dinesha	4638d 11h	/sdr_ctrl/trunk/verif/tb/
12	Column Bits are made programmable	dinesha	4638d 11h	/sdr_ctrl/trunk/verif/tb/
8	test bench files are added into SVN	dinesha	4642d 12h	/sdr_ctrl/trunk/verif/tb/
2		dinesha	4652d 12h	/sdr_ctrl/trunk/verif/tb/