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[/] [sdram_controller/] - Rev 13

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Rev Log message Author Age Path
13 Updated the top level testbench to reflect the fact that you need an
external DCM to run the controller with now.		 lynn0p 5362d 09h /sdram_controller/
12 1. rolled write recover clocks back to previous value and edited comments
2. increased 200us wait time to 300us in the init module		 lynn0p 5371d 12h /sdram_controller/
11 consolidated capture into one process and added comments lynn0p 5372d 08h /sdram_controller/
10 Fixes to more glitches uncovered during testing with my T80 SoC. Some
ops were getting dropped on the floor when the controller needed to do
an auto refresh.		 lynn0p 5372d 12h /sdram_controller/
9 Got rid of some redundant busy_n <= '0' statements lynn0p 5374d 00h /sdram_controller/
8 Changes made to integrate and test with my homebrew SoC design.

1. One DCM has been removed. Now requires a 100mhz clock fed in. Only
consumes one DCM, if you can find a 100mhz clock somewhere.
2. Small timing modifications to fix memory glitches between controller
and the t80 soft cpu I'm using.		 lynn0p 5374d 01h /sdram_controller/
7 Reformatted the comments so they fit in 80 columns lynn0p 5382d 05h /sdram_controller/
6 changes to reduce synthesizer warnings, removed unused signals, etc. lynn0p 5382d 10h /sdram_controller/
5 added header file for ddr.v lynn0p 5383d 05h /sdram_controller/
4 added testbench files to trunk lynn0p 5383d 05h /sdram_controller/
3 adding LGPLv3 license file lynn0p 5383d 06h /sdram_controller/
2 initial checkin lynn0p 5383d 06h /sdram_controller/
1 The project was created and the structure was created root 5383d 09h /sdram_controller/

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