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[/] [sdram_controller/] - Rev 24

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Rev Log message Author Age Path
24 Updating the .xise project file for Magnus lynn0p 5452d 13h /sdram_controller/
23 Adding Magnus' UCF and project config lynn0p 5454d 13h /sdram_controller/
22 Testbench was "broken" when I fixed controller for my SoC.
This "fixes" the testbench so it works again, so that the
testbench and my SoC both work.		 lynn0p 5455d 04h /sdram_controller/
21 1. Updated testbench to reflect lack of en signal
2. Deleted tarball and replaced it with a project file
and user constraints file		 lynn0p 5455d 05h /sdram_controller/
20 Got rid of the en signal, minor changes to eliminate synthesizer warnings. lynn0p 5457d 00h /sdram_controller/
19 Fix for the transparent latch warning. Z80 call stack pointer test code
still works.		 lynn0p 5457d 02h /sdram_controller/
18 Forgot to update the comments lynn0p 5458d 04h /sdram_controller/
17 When I moved the z80 callstack pointer into SDRAM from onchip SRAM,
very hilarious things started to happen. This removes the hilarity and
restores the previous somber mood. Depending on your own design you
may or may not want to update to this revision		 lynn0p 5458d 04h /sdram_controller/
16 Removed a redundant cap_en lynn0p 5460d 10h /sdram_controller/
15 - Adding a convenience project for building the testbench.
- Must have ISE 11.1 or higher and project is targeted at device type
xc3s500e-4fg320
- Pinouts may be incorrect for other board types. It is your
responsibility to check. Incorrect pinouts can lead to device damage.		 lynn0p 5461d 03h /sdram_controller/
14 Changed the clock period in the DCM generic to match 50mhz lynn0p 5461d 06h /sdram_controller/
13 Updated the top level testbench to reflect the fact that you need an
external DCM to run the controller with now.		 lynn0p 5461d 07h /sdram_controller/
12 1. rolled write recover clocks back to previous value and edited comments
2. increased 200us wait time to 300us in the init module		 lynn0p 5470d 10h /sdram_controller/
11 consolidated capture into one process and added comments lynn0p 5471d 06h /sdram_controller/
10 Fixes to more glitches uncovered during testing with my T80 SoC. Some
ops were getting dropped on the floor when the controller needed to do
an auto refresh.		 lynn0p 5471d 10h /sdram_controller/
9 Got rid of some redundant busy_n <= '0' statements lynn0p 5472d 22h /sdram_controller/
8 Changes made to integrate and test with my homebrew SoC design.

1. One DCM has been removed. Now requires a 100mhz clock fed in. Only
consumes one DCM, if you can find a 100mhz clock somewhere.
2. Small timing modifications to fix memory glitches between controller
and the t80 soft cpu I'm using.		 lynn0p 5472d 23h /sdram_controller/
7 Reformatted the comments so they fit in 80 columns lynn0p 5481d 04h /sdram_controller/
6 changes to reduce synthesizer warnings, removed unused signals, etc. lynn0p 5481d 08h /sdram_controller/
5 added header file for ddr.v lynn0p 5482d 03h /sdram_controller/

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