URL https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk

Subversion Repositories sha256_hash_core

[/] [sha256_hash_core/] [trunk/] [doc/] - Rev 9

Rev	Log message	Author	Age	Path
9	Optimized control logic; Changed 'ack' semantics to 'data write'. Changed error logic to detect invalid data writes.	jdoin	2802d 02h	/sha256_hash_core/trunk/doc/
8	Streamlined VHDL code to eliminate wire and combinational "initialization", changed all 'X' to 'U' on input signals, consisted comments.	jdoin	2872d 06h	/sha256_hash_core/trunk/doc/
6	Added Sim_test_1.png and Sim_test_8.png simulation pictures. Changed testbench for faster data input. Changed License text on all files. Consolidated file header info.	jdoin	2874d 17h	/sha256_hash_core/trunk/doc/
5	Reduced images sizes.	jdoin	2875d 19h	/sha256_hash_core/trunk/doc/
4	Reduced block diagrams image sizes.	jdoin	2875d 19h	/sha256_hash_core/trunk/doc/
3	Added GV_SHA256 block logic schematics.	jdoin	2875d 23h	/sha256_hash_core/trunk/doc/
2	SHA256 RTL code simulated and verified, to all NIST verification vectors. Pre-par synthesis show 74MHz clock rate, with no pipelining.	jdoin	2876d 00h	/sha256_hash_core/trunk/doc/