URL https://opencores.org/ocsvn/simpcon/simpcon/trunk

Subversion Repositories simpcon

[/] [simpcon/] [trunk/] [vhdl/] - Rev 29

Rev	Log message	Author	Age	Path
29	New and changed VHDL example files	martin	5518d 14h	/simpcon/trunk/vhdl/
26	New directory structure.	root	5601d 22h	/simpcon/trunk/vhdl/
24	remived JOP library references	martin	6138d 13h	/trunk/vhdl/
23	no message	martin	6140d 15h	/trunk/vhdl/
21	VHDL update	martin	6145d 05h	/trunk/vhdl/
20	VHDL update	martin	6145d 07h	/trunk/vhdl/
18	update from JOP	martin	6318d 06h	/trunk/vhdl/
17	SimpCon - Wishbone bridge	martin	6768d 14h	/trunk/vhdl/
16	Minimum SimpCon IO example	martin	6768d 14h	/trunk/vhdl/
15	ISA bus example (used to connect the CS8900 Ethernet chip)	martin	6768d 14h	/trunk/vhdl/
14	renamed to scio_min.vhd	martin	6768d 14h	/trunk/vhdl/
12	more IO examples	martin	6791d 17h	/trunk/vhdl/
11	no message	martin	6791d 17h	/trunk/vhdl/
10	Removed Flash ports	martin	6796d 09h	/trunk/vhdl/
9	Generic decoding and data mux	martin	6797d 19h	/trunk/vhdl/
8	Test IO slave and simple IO top	martin	6797d 21h	/trunk/vhdl/
7	Changed signal names to use the names from the specification.	martin	6799d 13h	/trunk/vhdl/
4	A 32-bis static RAM slave with read pipeline level 2	martin	6799d 23h	/trunk/vhdl/