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[/] [socgen/] - Rev 103

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Rev Log message Author Age Path
103 added user guide
resynced to local repository
jt_eaton 4631d 07h /socgen/
102 all ip-xact files now readable by kactus2 jt_eaton 4693d 03h /socgen/
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT
jt_eaton 4694d 05h /socgen/
100 created workspace prroject=fpga_mrisc for single compile
general cleanup
jt_eaton 4706d 12h /socgen/
99 moved all projects into /projects/opencores.org
added build_register
added fizzim
jt_eaton 4749d 05h /socgen/
98 removed unneeded sim jt_eaton 4785d 09h /socgen/
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims
jt_eaton 4785d 10h /socgen/
96 hierConnections now create ports jt_eaton 4859d 06h /socgen/
95 added first cut at busdefs
added clock reset enable pads and jtag_rpc
jt_eaton 4868d 04h /socgen/
94 socgen now supports both sim and syn views
now allow each xml file to set its destination
jt_eaton 4895d 05h /socgen/
93 build scripts now support model views
linting and coverage starting to work again
jt_eaton 4907d 17h /socgen/
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench
jt_eaton 4912d 18h /socgen/
91 fixed all sims, coverage not working jt_eaton 4920d 13h /socgen/
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4921d 05h /socgen/
89 removed unneeded debug directories jt_eaton 4942d 14h /socgen/
88 added xml files for test benches
added gEDA sym sch starter templates
jt_eaton 4942d 14h /socgen/
87 removed prebuilt geda schematics and symbols jt_eaton 4953d 06h /socgen/
86 split out all fpgas into families
added fpga pad_ring level
jt_eaton 4961d 03h /socgen/
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines
jt_eaton 4968d 02h /socgen/
84 removed unneeded files jt_eaton 5018d 08h /socgen/

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