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[/] [socgen/] - Rev 104

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Rev Log message Author Age Path
104 fixed search in preprocessor script
added initial orp_soc project
jt_eaton 4518d 20h /socgen/
103 added user guide
resynced to local repository
jt_eaton 4538d 21h /socgen/
102 all ip-xact files now readable by kactus2 jt_eaton 4600d 16h /socgen/
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT
jt_eaton 4601d 18h /socgen/
100 created workspace prroject=fpga_mrisc for single compile
general cleanup
jt_eaton 4614d 01h /socgen/
99 moved all projects into /projects/opencores.org
added build_register
added fizzim
jt_eaton 4656d 18h /socgen/
98 removed unneeded sim jt_eaton 4692d 22h /socgen/
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims
jt_eaton 4692d 23h /socgen/
96 hierConnections now create ports jt_eaton 4766d 19h /socgen/
95 added first cut at busdefs
added clock reset enable pads and jtag_rpc
jt_eaton 4775d 17h /socgen/
94 socgen now supports both sim and syn views
now allow each xml file to set its destination
jt_eaton 4802d 18h /socgen/
93 build scripts now support model views
linting and coverage starting to work again
jt_eaton 4815d 07h /socgen/
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench
jt_eaton 4820d 08h /socgen/
91 fixed all sims, coverage not working jt_eaton 4828d 02h /socgen/
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4828d 18h /socgen/
89 removed unneeded debug directories jt_eaton 4850d 03h /socgen/
88 added xml files for test benches
added gEDA sym sch starter templates
jt_eaton 4850d 03h /socgen/
87 removed prebuilt geda schematics and symbols jt_eaton 4860d 20h /socgen/
86 split out all fpgas into families
added fpga pad_ring level
jt_eaton 4868d 17h /socgen/
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines
jt_eaton 4875d 16h /socgen/

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