URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 113

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Rev	Log message	Author	Age	Path
113	started refactoring or1200	jt_eaton	4569d 21h	/socgen/
112	added more test sims removed unneeded files	jt_eaton	4579d 10h	/socgen/
111	split or1200 out into seperate test suite	jt_eaton	4581d 04h	/socgen/
110	split out more ip-xact components added sw sources	jt_eaton	4593d 02h	/socgen/
109	removed unused file	jt_eaton	4596d 02h	/socgen/
108	removed unneeded files	jt_eaton	4597d 08h	/socgen/
107	added designCfg files to all modules	jt_eaton	4597d 10h	/socgen/
106	checked in orp_soc project step 2	jt_eaton	4603d 03h	/socgen/
105	moved or1200_monitor from testbench to dut	jt_eaton	4606d 00h	/socgen/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4608d 00h	/socgen/
103	added user guide resynced to local repository	jt_eaton	4628d 01h	/socgen/
102	all ip-xact files now readable by kactus2	jt_eaton	4689d 20h	/socgen/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4690d 22h	/socgen/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4703d 06h	/socgen/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4745d 22h	/socgen/
98	removed unneeded sim	jt_eaton	4782d 02h	/socgen/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4782d 03h	/socgen/
96	hierConnections now create ports	jt_eaton	4856d 00h	/socgen/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4864d 21h	/socgen/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4891d 23h	/socgen/

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[/] [socgen/] - Rev 113

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