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[/] [socgen/] - Rev 114

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Rev Log message Author Age Path
114 moved or1200 connectivity out of verilog and into ip-xact
added or1200_boot block
removed force of 00 on lowest iwb_addr bits		 jt_eaton 4457d 01h /socgen/
113 started refactoring or1200 jt_eaton 4462d 17h /socgen/
112 added more test sims
removed unneeded files		 jt_eaton 4472d 06h /socgen/
111 split or1200 out into seperate test suite jt_eaton 4474d 01h /socgen/
110 split out more ip-xact components
added sw sources		 jt_eaton 4485d 22h /socgen/
109 removed unused file jt_eaton 4488d 22h /socgen/
108 removed unneeded files jt_eaton 4490d 04h /socgen/
107 added designCfg files to all modules jt_eaton 4490d 07h /socgen/
106 checked in orp_soc project step 2 jt_eaton 4496d 00h /socgen/
105 moved or1200_monitor from testbench to dut jt_eaton 4498d 20h /socgen/
104 fixed search in preprocessor script
added initial orp_soc project		 jt_eaton 4500d 21h /socgen/
103 added user guide
resynced to local repository		 jt_eaton 4520d 21h /socgen/
102 all ip-xact files now readable by kactus2 jt_eaton 4582d 17h /socgen/
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4583d 18h /socgen/
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4596d 02h /socgen/
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4638d 19h /socgen/
98 removed unneeded sim jt_eaton 4674d 23h /socgen/
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4675d 00h /socgen/
96 hierConnections now create ports jt_eaton 4748d 20h /socgen/
95 added first cut at busdefs
added clock reset enable pads and jtag_rpc		 jt_eaton 4757d 18h /socgen/

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